1. Field of the Invention
The present invention relates generally to a fabrication method of semiconductor devices, and more particularly to a fabrication method of flip chip semiconductor devices.
2. Description of Related Art
Different from a conventional wire bonding package structure, semiconductor chip of a flip chip package structure is mounted upside down to the substrate and electrically connected with the substrate through a plurality of bumps. Thus, the whole package structure becomes much smaller and thinner and meanwhile electrical performance thereof is improved.
FIGS. 1A to 1D show a fabrication method of a conventional flip chip package structure.
As shown in FIG. 1, a substrate 1 and a semiconductor chip 2 are provided, wherein the substrate 1 has a first surface 10 with a plurality of electrical connection pads 11, and the semiconductor chip 2 has an active surface 20 and a non-active surface 21, the active surface 20 having a plurality of bumps 22.
As shown in FIG. 1B, the semiconductor chip 2 is mounted upside down to the substrate 1 with the bumps 22 electrically connected with the electrical connection pads 11.
As shown in FIG. 1C, an underfilling process is performed so as to fill a filling material 23 between the active surface 20 of the semiconductor chip 2 and the first surface 10 of the substrate 1.
As shown in FIG. 1D, a molding process is performed such that an encapsulant 24 can be formed on the non-active surface 21 of the chip 2 and the first surface 10 of the substrate 1 to encapsulate the chip 2, the bumps 22 and the first surface 10 of the substrate 1.
By electrically connecting the bumps 22 of the chip 2 with the electrical connection pads 11 of the substrate 1, the above-described flip chip package structure achieves preferred electrical connection quality. However, the underfilling process is rather complicated, which adversely affects the efficiency of the fabrication process.
According to the above-described drawback, another fabrication method of a flip chip package structure is shown in FIGS. 2A to 2C.
As shown in FIG. 2A, a substrate 3 and a semiconductor chip 4 are provided. The substrate 3 has a first surface 30 with a plurality of electrical connection pads 31. An anisotropic conductive paste/film (ACP/ACF) is attached to the first surface 30, thereby forming a bonding layer 32 having conductive particles 321. The semiconductor chip 4 has an active surface 40 and a non-active surface 41, the active surface 40 having a plurality of bumps 42.
As shown in FIG. 2B, the semiconductor chip 4 is mounted upside down to the substrate 3 with the bumps 42 electrically connected with the electrical connection pads 31 through the conductive particles 321.
As shown in FIG. 2C, a molding process is performed such that an encapsulant 43 can be formed on the non-active surface 41 of the semiconductor chip 4 and the first surface 30 of the substrate 3 so as to encapsulate the semiconductor chip 4, the bumps 42 and the first surface 30 of the substrate 3.
Although the fabrication method can avoid the underfilling process by using the ACP/ACF, the ACP/ACF is quite expensive, which accordingly increases the fabrication cost and is not cost-effective.
In addition, when the ACP/ACF is used, the first surface 30 must be roughened to strengthen the bonding between the semiconductor chip 4 and the substrate 3, thereby complicating the fabrication process.
Therefore, how to improve electrical connection between the semiconductor chip and the substrate while simplifying the fabrication process and reducing the fabrication cost has become critical.